METHOD AND APPARATUS FOR PREEMPTIVE DESIGN VERIFICATION VIA PARTIAL PATTERN MATCHING

摘要

An approach is provided for preemptive design verification via partial pattern matching. Data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process is received. Data corresponding to a block of intellectual property including a layout design is received. At least a boundary of the layout design is scanned against the one or more problematic layout patterns. One or more partial matches of the one or more problematic layout patterns are identified at least at the boundary. Results are generated indicating the one or more partial matches.