发明名称 |
STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO |
摘要 |
The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. |
申请公布号 |
US2013026614(A1) |
申请公布日期 |
2013.01.31 |
申请号 |
US201213426386 |
申请日期 |
2012.03.21 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;YU CHEN-HUA;KUO TIN-HAO;CHEN CHEN-SHIEN;LII MIRNG-JI;WU SHENG-YU;LIN YEN-LIANG |
发明人 |
YU CHEN-HUA;KUO TIN-HAO;CHEN CHEN-SHIEN;LII MIRNG-JI;WU SHENG-YU;LIN YEN-LIANG |
分类号 |
H01L23/495;H01L21/98 |
主分类号 |
H01L23/495 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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