| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an optical transceiver capable of reducing the time required to initialize registers of circuit elements. <P>SOLUTION: An optical transceiver 1 comprises a CPU 3, an LDD+APC 13, a first CDR 17, and a second CDR 19. The CPU 3 is connected with each of the LDD+APC 13, the first CDR 17, and the second CDR 19 via an SPI interface. The CPU 3 simultaneously writes the same data to the LDD+APC 13, the first CDR 17, and the second CDR 19. <P>COPYRIGHT: (C)2013,JPO&INPIT |
