| 摘要 |
A process for making vertical electrical interconnections in a variety of integrated circuits and novel IC structures produced thereby wherein buried conductors are provided within a dielectric layer located above a silicon substrate having active or passive devices formed therein. Internal edges of only one or selected ones of the conductors are provided with an insulating coating, so that an adjacent via may be filled with a conductive material and still be electrically isolated from the one conductor or conductors. One or more vias are etched directly through the other buried conductor or conductors and also filled with a conductive material which electrically connects this buried conductor or conductors to both the substrate and to an upper level of metallization, and alternatively to intermediate conductors or other components. In this manner, lateral offset spacing requirements for masking and etching is minimized to thereby maximize the achievable component packing density within the IC structure being manufactured.
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