发明名称 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICALINTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
摘要 <p>INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFA method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit.(Fig 1)</p>
申请公布号 SG186536(A1) 申请公布日期 2013.01.30
申请号 SG20120024063 申请日期 2012.04.02
申请人 STATS CHIPPAC LTD 发明人 BYUNG JOON HAN;IN SANG YOON;JOHYUN BAE
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