MONOLITHIC RANK AND MULTIPLE RANK COMPATIBLE MEMORY DEVICE

摘要

PURPOSE: A memory device compatible with a mono rank and a multiple rank is provided to reduce a minimum transmission unit data size by adopting a threaded channel structure to output data to dual channels according to a plurality of active commands. CONSTITUTION: A memory device includes a first memory layer(12) and a second memory layer(14). The memory device receives an address signal or chip selection signals in response to a chip identification signal and a mode signal to determine a mono rank or multiple rank. The first memory layer and the second memory layer operate with the mono rank accessed according to the address signal or multiple rank accessed according to the chip selection signals.