发明名称 |
Solutions for on-chip modeling of open termination of fringe capacitance |
摘要 |
A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design.
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申请公布号 |
US8365117(B2) |
申请公布日期 |
2013.01.29 |
申请号 |
US201113158562 |
申请日期 |
2011.06.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;KEENE MICHAEL P.;WANG GUOAN;WOODS, JR. WAYNE H.;XU JIANSHENG |
发明人 |
KEENE MICHAEL P.;WANG GUOAN;WOODS, JR. WAYNE H.;XU JIANSHENG |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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