Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor

摘要

A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a load instruction and a data-dependent instruction to the instruction pipeline. Based on an operating mode, such as ECC mode or parity mode, the data-dependent instruction may execute in either the first of the second instruction pipeline stage. Further, the execution of the data-dependent instruction may depend on whether the most recently executed instruction was misaligned.