| 摘要 |
A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.
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