| 摘要 |
A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND cell unit by turning on the first and second select gate transistors, applying a predetermined voltage level on the source line, making a voltage level applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the second select gate transistor larger than that applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the first select gate transistor, and verifying data erase of the memory cell transistors.
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