发明名称 Processor and method for controlling storage-device test unit
摘要 A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred.
申请公布号 US8365027(B2) 申请公布日期 2013.01.29
申请号 US20090628470 申请日期 2009.12.01
申请人 FUJITSU LIMITED;YANAGIDA MASAHIRO 发明人 YANAGIDA MASAHIRO
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利