发明名称 Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
摘要 A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.
申请公布号 US8365127(B2) 申请公布日期 2013.01.29
申请号 US201213450317 申请日期 2012.04.18
申请人 RENESAS ELECTRONICS CORPORATION;HIRABAYASHI KEISUKE 发明人 HIRABAYASHI KEISUKE
分类号 G06F17/50 主分类号 G06F17/50
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