发明名称 |
Routing interconnect of integrated circuit designs |
摘要 |
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
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申请公布号 |
US8365128(B2) |
申请公布日期 |
2013.01.29 |
申请号 |
US20080347832 |
申请日期 |
2008.12.31 |
申请人 |
CADENCE DESIGN SYSTEMS, INC.;HE LIMIN;YAO SO-ZEN;DENG WENYONG;CHEN JING;CHAO LIANG-JIH |
发明人 |
HE LIMIN;YAO SO-ZEN;DENG WENYONG;CHEN JING;CHAO LIANG-JIH |
分类号 |
G06F17/50;H01L21/82 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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