发明名称 Test method of integrated circuit with random-number generation circuit and integrated circuit with random-number generation circuit
摘要 Random numbers output from a random-number generation circuit, for which an optimized control parameter is set, at a predetermined timing after power-on reset are obtained after each power-on reset, by repeating the power-on reset with respect to a system LSI for a preset number of times, and a test of the obtained predetermined number of random numbers is performed by using a test circuit incorporated in the system LSI to determine the quality of the random-number generation circuit incorporated in the system LSI.
申请公布号 US8364735(B2) 申请公布日期 2013.01.29
申请号 US20080252465 申请日期 2008.10.16
申请人 KABUSHIKI KAISHA TOSHIBA;NAKAKITA HIDEAKI 发明人 NAKAKITA HIDEAKI
分类号 G06F7/58;G06F1/02 主分类号 G06F7/58
代理机构 代理人
主权项
地址