发明名称 Stack package and method for selecting chip
摘要 <p>A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.</p>
申请公布号 KR101226270(B1) 申请公布日期 2013.01.25
申请号 KR20100130731 申请日期 2010.12.20
申请人 发明人
分类号 G11C5/02;G11C5/14 主分类号 G11C5/02
代理机构 代理人
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