发明名称 VERIFICATION APPARATUS, VERIFICATION PROGRAM AND VERIFICATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To shorten verification time by measuring an activating count of an asynchronous circuit selectively. <P>SOLUTION: A verification apparatus 1 comprises: an extraction part 1a to extract a structure type of an asynchronous path from a verification target 2; a specification part 1b to specify plural measurement spots including first and second measurement spots for the verification target 2 based on the extracted structure type of the asynchronous path; a detection part 1c to detect a signal propagation required number of cycles between the specified first and second measurement spots from the verification target 2; an assertion generation part 1d to generate an assertion to measure an activation count of the specified plural measurement spots using the detected signal propagation required number of cycles on an appointed timing; a measurement part 1e to measure the activation count of the specified plural measurement spots using the generated assertion during execution of an asynchronous simulation; and a comparing part 1f to compare the measurement result with an expected value. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013016025(A) 申请公布日期 2013.01.24
申请号 JP20110148377 申请日期 2011.07.04
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 TANIGAWA MOTOYA;IKEDA NORIYUKI;IKEUCHI KENTARO;TADA SACHIKO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址