发明名称 DECISION FEEDBACK EQUALIZER OPERABLE WITH MULTIPLE DATA RATES
摘要 Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.
申请公布号 US2013021074(A1) 申请公布日期 2013.01.24
申请号 US201113187693 申请日期 2011.07.21
申请人 NATIONAL SEMICONDUCTOR CORPORATION;FINN STEVEN E.;CHANDRAMOULI SOUMYA 发明人 FINN STEVEN E.;CHANDRAMOULI SOUMYA
分类号 H03L7/00 主分类号 H03L7/00
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