发明名称 |
METHODS AND STRUCTURE FOR SOURCE SYNCHRONOUS CIRCUIT IN A SYSTEM SYNCHRONOUS PLATFORM |
摘要 |
Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.
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申请公布号 |
US2013021059(A1) |
申请公布日期 |
2013.01.24 |
申请号 |
US201113185019 |
申请日期 |
2011.07.18 |
申请人 |
LSI CORPORATION;SINGH DEVENDRA BAHADUR;DATE ANAND SADASHIV;SABNIS HRISHIKESH SURESH |
发明人 |
SINGH DEVENDRA BAHADUR;DATE ANAND SADASHIV;SABNIS HRISHIKESH SURESH |
分类号 |
H03K19/177 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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