| 摘要 |
To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8xSi+1 produced by a bit shifter to output the sum 9xSi+1 to an adder. The adder adds the sum (9xSi+1) supplied thereto by the adder to a sum (9xSi) supplied thereto after being delayed by a delay element and outputs the result of the addition (9xSi+9xSi+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9xSi+9xSi+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9xSi-9xSi+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9xSi-9xSi+1+Si+2) supplied thereto by the adder by four bits toward the LSB and outputs the right-shifted value (Si-1-9xSi-9xSi+1+Si+2)/16 to a second interpolation circuit as a first interpolation value Si' along with the sampled values Si and Si+1. As a result, the number of sampled values seemingly appears increased.
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