| 摘要 |
<p>A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings of transistors undergoing programming operations with significant variations in potential. Each string has a first select gate (105), a plurality of floating gates (102), and a second select gate. The floating gates are formed between shallow trench isolation areas (104) and wordlines (106) extend across adjacent strings and extend between the floating gates into the shallow trench isolation areas thereby shielding the floating gates from variations in potential of adjacent memory cells.</p> |
