发明名称 |
Delay-locked-loop circuit, semiconductor device and memory system having the delay-locked-loop circuit |
摘要 |
A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
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申请公布号 |
US8358547(B2) |
申请公布日期 |
2013.01.22 |
申请号 |
US20100979814 |
申请日期 |
2010.12.28 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD.;CHOI JUNG-HWAN |
发明人 |
CHOI JUNG-HWAN |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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