| 摘要 |
[课题]不降低筛选精度，简化半导体积体电路之设计;。;[解决手段]藉由半导体积体电路设计资料来生成半导;体积体电路之实体布局之际的半导体积体电路之设计方法，其特征为，具有：元件配置配线工程，系将生成实体布局所需之元件予以配置并配线；和设计规则检查工程，系参照着设计规则检查用之规则函式库，将含有实体布局之元件的第2实体布局之形状，加以验证；和光罩资料处理工程，系当不满足前记设计规则时，进行身为验证对象之第2实体布局的光罩资料处理；和光罩资料作成工程，使用光罩资料处理工程中进行过光罩资料处理的第2实体布局，来作成光罩资料；和光罩资料作成工程，系当满足设计规则时，使用第2实体布局，来作成对应于实体布局的光罩资料。;A method of designing a semiconductor integrated circuit includes a cell arranging and wiring step of arranging and wiring cells for creating a physical layout, a design-rule checking step of verifying a shape of a second physical layout including the cells of the physical layout with reference to a ruIe library for design rule check, a mask-data creating step of creating mask data corresponding to the physical layout using the second physical layout when the design rule is satisfied in the design-rule checking step, a mask-data processing step of performing, when the design rule is not satisfied in the design-rule checking step, mask data processing for the verification-object second physical layout, and a mask-data creating step for creating mask data corresponding to the physical layout using the second physical layout subjected to the mask data processing in the mask-data processing step. |
