发明名称 Nanowire Memory
摘要 Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.
申请公布号 KR101217574(B1) 申请公布日期 2013.01.18
申请号 KR20090053397 申请日期 2009.06.16
申请人 发明人
分类号 H01L29/78 主分类号 H01L29/78
代理机构 代理人
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