发明名称 MEMORY CONTROL APPARATUS, INFORMATION PROCESSING APPARATUS, AND MEMORY CONTROL METHOD
摘要 A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.
申请公布号 US2013016726(A1) 申请公布日期 2013.01.17
申请号 US201213542139 申请日期 2012.07.05
申请人 NUMAKURA SATORU;IKEDA JUNICHI;SUZUKI MITSURU;TAKEO KOJI;SATOH TETSUYA;TAKAHASHI HIROYUKI 发明人 NUMAKURA SATORU;IKEDA JUNICHI;SUZUKI MITSURU;TAKEO KOJI;SATOH TETSUYA;TAKAHASHI HIROYUKI
分类号 H04L0012/000056 主分类号 H04L0012/000056
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