| 摘要 |
In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to standard. During the test mode, a DQ receiver is supplied with the operating clock signal instead of the DQS signal. A downstream memory element is bridged by a direct signal path. To change over, multiplexers/demultiplexers driven by the test mode control signal are provided. The data signal supplied to the memory cell array is available immediately after a write command has been applied to the memory cell array.
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