A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.
申请公布号
WO2012092496(A3)
申请公布日期
2013.01.17
申请号
WO2011US67905
申请日期
2011.12.29
申请人
SPANSION LLC;FANG, SHENQING;CHEN, TUNG-SHENG;CHEN, CHUN
