发明名称 |
COMPACT AND ROBUST LEVEL SHIFTER LAYOUT DESIGN |
摘要 |
Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first Nwell and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well. |
申请公布号 |
WO2013010043(A1) |
申请公布日期 |
2013.01.17 |
申请号 |
WO2012US46562 |
申请日期 |
2012.07.12 |
申请人 |
QUALCOMM INCORPORATED;DATTA, ANIMESH;GOODALL III, WILLIAM JAMES |
发明人 |
DATTA, ANIMESH;GOODALL III, WILLIAM JAMES |
分类号 |
H01L27/02;H03K19/0185 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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