发明名称 CIRCUIT CONFIGURATIONS TO REDUCE SNAPBACK OF A TRANSIENT VOLTAGE SUPPRESSOR
摘要 This invention discloses a transient voltage suppressing (TVS) circuit that includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. The triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in an N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
申请公布号 US2013016446(A1) 申请公布日期 2013.01.17
申请号 US201213351186 申请日期 2012.01.16
申请人 MALLIKARJUNASWAMY SHEKAR 发明人 MALLIKARJUNASWAMY SHEKAR
分类号 H01L21/332;H02H9/04 主分类号 H01L21/332
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