发明名称 |
FET eDRAM TRENCH SELF-ALIGNED TO BURIED STRAP |
摘要 |
A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
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申请公布号 |
US2013015515(A1) |
申请公布日期 |
2013.01.17 |
申请号 |
US201113182738 |
申请日期 |
2011.07.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;ANDERSON BRENT A.;BARTH, JR. JOHN E.;NOWAK EDWARD J.;RANKIN JED H. |
发明人 |
ANDERSON BRENT A.;BARTH, JR. JOHN E.;NOWAK EDWARD J.;RANKIN JED H. |
分类号 |
H01L21/8242;H01L27/06 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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