Memory architecture of array with single gate memory devices

摘要

A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged orthogonally over the plurality of vertically stacked NAND strings, and a plurality of vertical columns of conductive gate material electrically coupled to the plurality of word lines. The plurality of vertically stacked NAND strings are with vertically stacked semiconductor strips having opposite sides including a first side and a second side. The vertical columns in the plurality of vertical columns are gates to only one side of the first side and the second side of the opposite sides of the vertically stacked semiconductor strips. The vertical columns in the plurality of vertical columns are gates to adjacent stacks in the plurality of vertically stacked NAND strings.

主权项

1. A method for manufacturing a nonvolatile memory array, comprising:
forming a plurality of layers of a semiconductor material alternating with insulating layers on a substrate; etching the plurality of layers to define a first plurality of trenches and a second plurality of trenches, the first plurality of trenches formed in a first patterned etch and the second plurality of trenches formed in a second patterned etch defining a plurality of stacks of strips of the semiconductor material, the first plurality of trenches interleaved with the second plurality of trenches, a first width of the first plurality of trenches being wider than a second width of the second plurality of trenches; forming, in the first plurality of trenches and not in the second plurality of trenches, a conformal layer of nonvolatile memory material that stores data as part of nonvolatile memory cells in the nonvolatile memory array; forming, in the first plurality of trenches, a plurality of vertical columns of conductive gate material that are gates to stacks of the plurality of stacks on first and second opposite sides of trenches of the first plurality of trenches; and forming a plurality of word lines orthogonally over the plurality of stacks of strips, the plurality of word lines electrically coupled with the plurality of vertical columns, establishing memory cells for a plurality of vertically stacked NAND strings.