| 摘要 |
In a wireless video display system requiring synchronisation between the respective clocks of a RF video send node (102) and a receive node (103), a Phase Locked Loop (PLL) in a source part 206 of the sender node generates HDMI video data in synchronism with a source clock including timestamps (306) from a Vsync sampler 217, and a similar source part in the receiver node uses the same PLL via the timestamp information in the received video data to synchronise a local clock via a RX synchro manager 213, avoiding the need for an additional PLL.
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