发明名称 |
Dynamic RAM Phy interface with configurable power states |
摘要 |
A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
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申请公布号 |
US8356155(B2) |
申请公布日期 |
2013.01.15 |
申请号 |
US20100910412 |
申请日期 |
2010.10.22 |
申请人 |
ADVANCED MICRO DEVICES, INC.;SEARLES SHAWN;HUMPHRIES NICHOLAS T.;AMICK BRIAN W.;REEVES RICHARD W.;CHO HANWOO;PETTYJOHN RONALD L. |
发明人 |
SEARLES SHAWN;HUMPHRIES NICHOLAS T.;AMICK BRIAN W.;REEVES RICHARD W.;CHO HANWOO;PETTYJOHN RONALD L. |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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