发明名称 |
Method for fabricating low-k dielectric and Cu interconnect |
摘要 |
A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
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申请公布号 |
US8354346(B2) |
申请公布日期 |
2013.01.15 |
申请号 |
US201113179139 |
申请日期 |
2011.07.08 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;CHEN CHIH-HAO;CHOU CHIA-CHENG;LIANG MING-CHUNG;LIN KENG-CHU;LEE TZU-LI |
发明人 |
CHEN CHIH-HAO;CHOU CHIA-CHENG;LIANG MING-CHUNG;LIN KENG-CHU;LEE TZU-LI |
分类号 |
H01L21/302;H01L21/461 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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