发明名称 |
Negotiation between multiple processing units for switch mitigation |
摘要 |
A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.
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申请公布号 |
US8356200(B2) |
申请公布日期 |
2013.01.15 |
申请号 |
US20080239618 |
申请日期 |
2008.09.26 |
申请人 |
APPLE INC.;BJEGOVIC NEBOJSA;HEPPOLETTE VANESSA CRISTINA |
发明人 |
BJEGOVIC NEBOJSA;HEPPOLETTE VANESSA CRISTINA |
分类号 |
G06F13/42;G06F13/14;G06F15/00;H04L7/00 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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