发明名称 CPU connection circuit, data processing apparatus, arithmetic processing device, portable communication terminal using these modules and data transfer method
摘要 There are provided a CPU connection circuit and a method wherein the CPU connection circuit is a circuit to be employed by two CPUs by alternately conducting a changeover between two buffers disposed therebetween to prevent an event that data processing cannot be fully executed by the CPU on the receiving side. There is included a memory controller 303 which monitors whether or not an amount of data stored by a CCPU 1 in either one of buffers 301 and 302 reaches a predetermined threshold value; when the amount of data stored by the CCPU 1 in the buffer 301, 302 reaches the threshold value, the memory controller 303 requests an ACPU 2 to acquire the data stored in the buffer and changes the storage destination of data from the CCPU to the other one of the buffers; the threshold value is a value more than a unit quantity of data which the CCPU 1 sends to the buffer 301, 302.
申请公布号 US8355326(B2) 申请公布日期 2013.01.15
申请号 US20070374949 申请日期 2007.07.25
申请人 NEC CORPORATION;NAKAGAWA TAKAO;TACHIKAWA TAKASHI;NAKAMURA NAOYUKI;TSUKAMOTO TADASHI;HOSOI TOSHIKATSU;KURAKANE HIROSHI 发明人 NAKAGAWA TAKAO;TACHIKAWA TAKASHI;NAKAMURA NAOYUKI;TSUKAMOTO TADASHI;HOSOI TOSHIKATSU;KURAKANE HIROSHI
分类号 H04L12/54 主分类号 H04L12/54
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