| 摘要 |
An LDPC(Low Density Parity Check) encoder is provided to calculate plural parity bits using a single block manipulation process by using a triangular matrix. An LDPC encoder includes a manipulation processor(910), an adder module(920), a memory(930), a first scheduler(940), a second scheduler(950), and a controller(960). The manipulation processor processes a systematic part in a parity check matrix. The adder module accumulates the output from the manipulation processor. The memory stores the output from the adder module. The first scheduler performs a data process on a result from the memory. The second scheduler performs the data process on the output from the adder module according to a structure of the parity check matrix. The controller controls the schedulers. |
