发明名称 Yield based flop hold time and setup time definition
摘要 Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.
申请公布号 US8356263(B1) 申请公布日期 2013.01.15
申请号 US201113172951 申请日期 2011.06.30
申请人 QUALCOMM INCORPORATED;ZHANG XIAONAN;BAI XIAOLIANG;PATEL PRAYAG B. 发明人 ZHANG XIAONAN;BAI XIAOLIANG;PATEL PRAYAG B.
分类号 G06F9/455 主分类号 G06F9/455
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