发明名称 Method for reducing power consumptiom to multi-port memory device of memory link architecture
摘要 A memory link architecture (MLA) comprises a multi-port memory device, a memory controller, and a nonvolatile memory. The MLA can perform a sleep switching control operation or a memory management operation to reduce power consumption based on commands received from a host processor and/or automatic control methods.
申请公布号 KR101222082(B1) 申请公布日期 2013.01.14
申请号 KR20100124976 申请日期 2010.12.08
申请人 发明人
分类号 G06F1/32;G06F13/10 主分类号 G06F1/32
代理机构 代理人
主权项
地址