| 摘要 |
There is provided a variable delay circuit to be implemented in an integrated circuit, the variable delay circuit including: a variable delay assigning section that assigns a variable time delay to an input signal in an actual operation of the integrated circuit, the variable time delay being varied within a predetermined range in accordance with a time delay inherent in an implementation level; and a verification delay assigning section that assigns a predetermined fixed time delay to the input signal in low-speed logic verification and/or in a low-speed selection test of the integrated circuit. For example, the time delay assigned by the verification delay assigning section is larger than a maximum value of the time delay assigned by the variable delay assigning section. |
