| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce such possibility that an EM verification result is turned to be NG in the case of designing a semiconductor integrated circuit. <P>SOLUTION: The design method of a semiconductor integrated circuit includes: a step (A) of creating a net list with parasitic RC by adding a temporary parasitic capacity and 0 or more pieces of temporary parasitic resistances to a net in the net list of a design object circuit; a step (B) of executing circuit simulation by using the net list with parasitic RC, and calculating element terminal currents to be the currents of each element terminal connected to the net and parasitic capacity currents to be the currents of the temporary parasitic capacity; a step (C) of changing the value of the element terminal currents by distributing the parasitic capacity currents to each element terminal; and a step (D) of calculating wiring width constraint relating to the net on the basis of the changed element terminal currents. <P>COPYRIGHT: (C)2013,JPO&INPIT |
