发明名称 |
DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER |
摘要 |
A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.
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申请公布号 |
US2013009685(A1) |
申请公布日期 |
2013.01.10 |
申请号 |
US201213613342 |
申请日期 |
2012.09.13 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD.;BAE SEUNG JUN;PARK KWANG IL;KIM YOUNG-SIK;KWAK SANG HYUP |
发明人 |
BAE SEUNG JUN;PARK KWANG IL;KIM YOUNG-SIK;KWAK SANG HYUP |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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