<p>Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.</p>
申请公布号
WO2013006702(A1)
申请公布日期
2013.01.10
申请号
WO2012US45559
申请日期
2012.07.05
申请人
ADVANCED MICRO DEVICES, INC.;BAILEY, DANIEL W.;ROGERS, AARON S.;MONTANARO, JAMES J.;BURGESS, BRADLEY G.;HANNAN, PETER J.
发明人
BAILEY, DANIEL W.;ROGERS, AARON S.;MONTANARO, JAMES J.;BURGESS, BRADLEY G.;HANNAN, PETER J.