| 发明名称 |
LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE |
| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress variation in characteristics of a transistor which is caused by double patterning. <P>SOLUTION: A plurality of gate electrode patterns 10-15 arranged in parallel to each other are set to be a first pattern which is formed in a first exposure step of a double patterning and to be a second pattern formed in a second exposure step, alternately (step S1). A circuit containing a transistor pair in which the first pattern and the second pattern are connected in parallel to each other is laid out (step S2), thereby variation in characteristics of a transistor caused by the double patterning is suppressed. <P>COPYRIGHT: (C)2013,JPO&INPIT |
| 申请公布号 |
JP2013008926(A) |
申请公布日期 |
2013.01.10 |
| 申请号 |
JP20110142067 |
申请日期 |
2011.06.27 |
| 申请人 |
FUJITSU SEMICONDUCTOR LTD |
发明人 |
HIRAMOTO TAKANORI;HINO TOSHIO;SAKATA TAKESHI;MIZUNO YUTAKA;OGATA KATSUYA |
| 分类号 |
H01L21/82;G03F1/70;H01L21/822;H01L27/04 |
主分类号 |
H01L21/82 |
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