| 摘要 |
In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.
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