发明名称
摘要 <p>When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed.</p>
申请公布号 JP5116337(B2) 申请公布日期 2013.01.09
申请号 JP20070092352 申请日期 2007.03.30
申请人 发明人
分类号 G11C16/02 主分类号 G11C16/02
代理机构 代理人
主权项
地址