发明名称 Method for manufactoring matrix display device with damascene wiring lines
摘要 <p>The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid-crystal display device, line resistance is decreased. <IMAGE></p>
申请公布号 EP1349208(B1) 申请公布日期 2013.01.09
申请号 EP20030006774 申请日期 2003.03.25
申请人 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 发明人 TAKAYAMA, TORU;YAMAZAKI, SHUNPEI
分类号 H01L21/768;G02F1/1362;H01L21/77;H01L21/84;H01L27/12;H01L27/32 主分类号 H01L21/768
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