发明名称
摘要 <p>Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.</p>
申请公布号 JP5112180(B2) 申请公布日期 2013.01.09
申请号 JP20080153155 申请日期 2008.06.11
申请人 发明人
分类号 G11C16/02;G11C16/04;G11C16/06;H01L21/336;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C16/02
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