| 摘要 |
PURPOSE: A memory device for implementing a parallel test mode of a memory cell is provided to implement normal parallel test without defects by removing a floating state of a lower selection data input and output line which loads a second data of a lower bank when a first data and the second data are read with a bit line unit in a parallel test. CONSTITUTION: A bank includes an upper bank with a first cell matrix storing a first data and a lower bank with a second cell matrix storing a second data. A selection switch implement a switching operation to load the first data by receiving a first selection signal(Yi) and a switching operation to load the second data by receiving a second selection signal. A selection data input and output line includes an upper selection data input and output line to load the first data and a lower selection data input and output line to load the second data. A Yi delay signal generating unit(530) precharges the lower selection data input and output line by inputting a Yi delay signal(Yi-D) to a selection switch. [Reference numerals] (AA) Yi<0> delay signal generating unit; (BB) Yi<1> delay signal generating unit; (CC) Yi<n> delay signal generating unit |
