发明名称
摘要 PROBLEM TO BE SOLVED: To reduce display irregularity on a display panel. SOLUTION: An LCD panel 10 comprises: a plurality of pixels 16 in which a plurality of source lines S1, S2, ... and a plurality of gate lines G1, G2, ... are arranged like a matrix and one source line is arranged so as to be shared by two adjacent pixels; and a plurality of TFTs 18 arranged according to respective pixels to control each pixel according to a selection state of the source lines and the gate lines corresponding to each pixel, wherein a plurality of dummy drain lines D with fixed potential are wired between two pixels including no source line between them by a form similar to the source lines, so that the generation of parasitic capacitance between pixels is suppressed and display irregularity is reduced. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP5115001(B2) 申请公布日期 2013.01.09
申请号 JP20070089666 申请日期 2007.03.29
申请人 发明人
分类号 G09G3/20;G02F1/1362;G09F9/30;G09G3/36 主分类号 G09G3/20
代理机构 代理人
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