发明名称 |
Method and system to reduce the power consumption of a memory device |
摘要 |
A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.
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申请公布号 |
US8352683(B2) |
申请公布日期 |
2013.01.08 |
申请号 |
US20100823047 |
申请日期 |
2010.06.24 |
申请人 |
INTEL CORPORATION;COHEN EHUD;MARGULIS OLEG;SADE RAANAN;SHWARTSMAN STANISLAV |
发明人 |
COHEN EHUD;MARGULIS OLEG;SADE RAANAN;SHWARTSMAN STANISLAV |
分类号 |
G06F12/00;G06F1/00;G06F13/00;G06F13/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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